您的当前位置：首页 DDR2_design_and_layout

DDR2_design_and_layout

来源：要发发知识网

Freescale SemiconductorApplication Note

Document Number:AN2910

Rev. 2, 03/2007

Hardware and Layout Design

Considerations for DDR2 SDRAM Memory Interfaces

DSD Applications

Freescale Semiconductor, Inc.Austin, TX

The design guidelines presented in this document apply to products that leverage the DDR2 SDRAM IP core, and they are based on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.

Because numerous memory topologies and interface

frequencies are possible on the DDR2 SDRAM interface, Freescale highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.

12345

678

Contents

Designer’s Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . .2Termination Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 7VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7VTT Voltage Rail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Layout Guidelines for the Signal Groups . . . . . . . . . . .85.1 Data—MDQ[0:63], MDQS[0:8], MDM[0:8],

MECC[0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95.2 Layout Recommendations . . . . . . . . . . . . . . . . . . .9Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Designer’s Checklist

1Designer’s Checklist

Table1. DDR2 Designer’s Checklist

Item

Description

Yes/No

In the following checklist, some of the items are phrased as question, others as requirements. In all cases, we recommend that you consider the line item and check it off in the rightmost column of Table1.

Simulation

Have optimal termination values, signal topology, trace lengths been determined through simulation for each signal group in the memory implementation? If on-die termination is used at both the memories and the controller, no additional termination is required for the data group.Four unique groupings exist:

(1). Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0) (2). Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.(3). Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)(4). Clock Group: MCK(5:0) and MCK(5:0)

These groupings assume a full 72-bit data implementation (-bit + 8 bit of ECC). Some products may only implement 32-bit data and may choose to have less MCS MCKE, and MODT signals. Secondly, some products support the optional MAPAR_OUT and MAPAR_ERR for registered DIMMs. In such cases, MAPAR_OUT should be treated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.

Does the selected termination scheme meet the AC signaling parameters (voltage levels, slew rate, overshoot/undershoot) across all memory chips in the design?

Termination Scheme

It is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards.

Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are used for the Address/CMD and the control groups. Consequently, differing termination techniques may also prove valid and useful. However, they are left to the designer to validate through simulation.

3.4.

Is the worst case power dissipation for the termination resistors within the manufacturer’s rating for the selected devices? See Section2, “Termination Dissipation”.

If resistor packs are used, have data lanes been isolated from the other DDR2 signal groups?

Note: Because on-die termination is the preferred method for DDR2 data signals, external resistors for the data group should not be required. This item would only apply if the ODT feature is not used.Have VTT resistors been properly placed? The RT terminators should directly tie into the VTT island at the end of the memory bus.

If series damping (RS) terminators are used (not seen as mainstream approach), were they placed close to the first memory DIMM?

For discrete implementations—Placement of the series damping resistor (RS) for the data group is left to the board designer. This trade-off is optimal signal integrity for both reads/writes (RS in middle) versus ease of layout routing (RS placed closer to memory devices).

5.6.

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Designer’s Checklist

Table1. DDR2 Designer’s Checklist (continued)

Item7.

Description

For address and command signals, the Micron compensation cap scheme is another optional termination method for improving eye apertures for a heavily loaded system (> 18 memory chips). For details on this termination scheme refer to DDR533 Memory Design for Two-DIMM Unbuffered Systems, located on Micron’s web site. For lightly and medium loaded memory subsystems (4–18 chips), the compensation cap method is not as beneficial.

If used, are the CCOMP capacitors placed within 0.5 inch of the first memory bank?

Is the differential terminator present on the clock lines for discrete memory populations? (DIMM modules contain this terminator.) Nominal range => 100-120 Ω.

Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are used, the cap should be placed as closely as possible to the DIMM connector. If discrete devices are used, the cap should be placed as closely as possible to the discrete devices.

Recommendation—Place 0-Ω resistors on the DDR2 clock lines (near the driver). Such flexibility allows the clock lengths to be extended (if needed) during the prototyping phase.

Yes/No

8.9.

10.

VTT Related Items

11.12.13.

Has the worst case current for the VTT plane been calculated based on the design termination scheme? See Section2, “Termination Dissipation”.

Can the VTT regulator support the steady state and transient current needs of the design?Has the VTT island been properly decoupled with high frequency decoupling? At least 1 low ESL cap, or 2 standard decoupling caps for each 4-pack resistor network (or every 4 discrete resistors) should be used. In addition, at least one 4.7-μF cap should be at each end of the VTT island.Note: This recommendation is based on a top-layer VTT surface island (lower inductance). If an internal split is used, more capacitors may be needed to handle the transient current demands.Has the VTT island been properly decoupled with bulk decoupling? At least 1 bulk cap (100–220μF) capacitor should be at each end of the island.

Has the VTT island been placed at the end of the memory channel and as closely as possible to the last memory bank? Is the VTT regulator placed in close proximity to the island?Is a wide surface trace (~150 mils) used for the VTT island trace?

If a sense pin is present on the VTT regulator, is it attached in the middle of the island?

14.15.16.17.VREF

18.19.20.21.22.23.Routing

Is VREF routed with a wide trace? (Minimum of 20–25 mil recommended.)

Is VREF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from VREF to other traces. If possible, isolate VREF with adjacent ground traces.

Is VREF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.

Does the VREF source track variations in VDDQ, temperature, and noise as required by the JEDEC specification?

Does the VREF source supply the minimal current required by the system (memories + processor)?If a resistor divider network is used to generate VREF, are both resistors the same value and 1% tolerance?

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Designer’s Checklist

Table1. DDR2 Designer’s Checklist (continued)

Item24.

Description

Suggest routing order within the DDR2 interface:

1) Data, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power

This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layer on which clocks are freely routed.

Global items—

•Do not route any DDR2 signals overs splits or voids.

•Traces routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the reference plane.

•Allow no more than 1/2 of a trace width to be routed over via antipad.

When routing the data lanes, route the outermost (that is, longest lane first) because this determines the amount of trace length to add on the inner data lanes.

Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?The DDR2 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given byte lane should be routed on the same critical layer with the same via count. Note: Some product implementations may only implement a 32-bit wide interface.Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)

To facilitate fan-out of the DDR2 data lanes (if needed), alternate adjacent data lanes onto different critical layers? See Figure1 and Figure2.

Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on the initial hardware prototypes.

DDR2 data group—Impedance range and spacing

•Single-ended target Impedance = 50–60 Ω range (MDQ, MDM)

•Differential target impedance = 100–120 Ω range (MDQS, MDQS) Note: Some product implementations may support only the single-ended version of the strobe.

•Referenced to a solid ground plane, thereby providing a low-impedance path for return currents. •Trace space to other non-DDR2 data groups = 25 mil.

•Trace space requirements within the DDR2 data group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.Across all DDR2 data lanes, are all the data lanes matched to within 0.5 inch?

Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumes highest frequency operation.)

When adding trace lengths to any of the DDR2 signal groups, ensure that there is at least 25 mils between serpentine loops that are in parallel.

Yes/No

25.

26.27.28.

29.

30.31.32.

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Designer’s Checklist

Table1. DDR2 Designer’s Checklist (continued)

Item33.

Description

MDQS/MDQS differential strobe routing

Note: Some product implementations may support only the single-ended version of the strobe. •Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MDQS/ MDQS pair to be within 10 mils.

•Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.

•Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock chips.

•Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)

•Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the same critical layer as its associated data lane.DDR2 address/command group—Impedance range and spacing •Single-Ended Target Impedance = 50–60 Ω range •Match all traces to within 100 mils

•Referenced to a contiguous 1.8-V power reference (DIMM implementations currently do this) •Referenced to a contiguous 1.8-V power reference or ground plane (discrete implementations) •Trace space to other non-DDR2 address/cmd signals = 25 mil.

•Trace space requirements within the DDR2 address/cmd group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.DDR2 control group—Impedance range and spacing •Single-Ended Target Impedance = 50–60 Ω range •Match all traces to within 100 mils

•Trace space requirements within the DDR2 control group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.Are the DDR2 signal groups tuned to the clock reference? Because this is loading and topology dependent, the variance around the clock should be determined by simulation.

Secondly, in multi-bank systems, are the address and command signals loaded more heavily than the control signals (CS, ODT, CKE)?Specifically:

•Are the setup/hold optimized for the addr/cmd group?

•Are the steup/hold optimized for the control group (CS, ODT, CKE)?

•Is the write data delay window met (tDQSS)? This is the relationship between the data strobes and clocks as specified by the JEDEC DDR2 specification.Are the DDR2 differential clocks properly routed?

•Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MCK/ MCK pair to be within 10 mils.

•Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.

•Avoid routing differential pairs adjacent to noisy signals lines or high speed switching devices such as clock chips.

•Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)

•Do not divide the two halves of the diff pair between layers. Route MCK/MCK pair on the same critical layer. Are all clock pairs routed on the same critical layer (one referenced to a solid ground plane)?Are all clock pairs properly trace matched to within 25 mils of each other?

Yes/No

34.

35.

36.

37.

38.39.

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Designer’s Checklist

Table1. DDR2 Designer’s Checklist (continued)

Item40.41.42.DescriptionThe space from one differential pair to any other trace (this includes other differential pairs) should be at least 25 mils.If unbuffered DIMM modules are used, are all three required clock pairs per DIMM slot connected?If the optional 0-Ω resistors are used (as noted in item 10), use ground stitching vias near the resistors.Yes/NoMODT/MDIC Related Items43.Are the MODT signals connected correctly? MODT(0), MCS(0), MCKE(0) should all go to the same physical memory bank.MODT(1), MCS(1), MCKE(1) should all go to the same physical memory bank.MODT(2), MCS(2), MCKE(2) should all go to the same physical memory bank.MODT(3), MCS(3), MCKE(3) should all go to the same physical memory bank.Is MDIC0 connected to ground via an 18.2-Ω precision 1% resistor? Is MDIC1 connected to DDR power via an 18.2-Ω precision 1% resistor?44.Miscellaneous Items45.Keep the memory channel (area between controller and the memory) free of noisy and high frequency components (ideal case is to place only memory terminators and decoupling within this area).Are the power-on reset config pins properly set for the correct DDR type?Note: Not all Freescale products support external power-on reset configuration pins for selecting the DDR type. Therefore, this item does not apply to all Freescale products.46.Registered DIMM Topologies (All items above still apply)47.For memory implementations that use registered DIMM modules, the board designer should attach a reset signal to the DIMM sockets. This reset signal should be derived from a ‘power good’ monitor status circuit.Though registered DIMMs require only a single clock per bank, all DDR2 clock pairs at the DIMM connector should be attached (analogous to unbuffered DIMMs) so the design can also support unbuffered DIMMs with minimal changes.If the controller supports the optional MAPAR_OUT and MAPAR_ERR signals, ensure that they are hooked up as follows: MAPAR_OUT (from the controller) => PAR_IN (at the RDIMM).ERR_OUT (from the RDIMM) => MAPAR_ERR (at the controller).MAPAR_ERR is an open drain output from registered DIMMs. Ensure that a 4.7K pull-up to 1.8 V is present on this signal.48.49.50.Discrete Memory Topologies (All items above still apply with exception of registered DIMM items)51.52.Construct the signal routing topologies for the groups like those found on unbuffered DIMM modules (that is, proven JEDEC topologies).When placing components, optimize placement of the discretes to favor the data bus (analogous to DIMM topologies).Optional: Pin-swap within a given byte lane to optimize the data bus routes further.Caution: Do not swap individual data bits across different byte lanes.Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Termination Dissipation

Table1. DDR2 Designer’s Checklist (continued)

Item53.

Description

If a single bank of x16 devices is used, let the DDR2 clocks be point-to-point. Place the series damping resistor (RS) close to the source and the differential terminator (RDIFF) at the input pins of the discretes.

If more than 5 discretes are used, construct the clocks like those on unbuffered DIMM modules. Alternatively, place an external PLL between the controller and the memory to generate the additional clocks.

If multiple physical banks are needed, double stack (top and bottom) the banks to prevent lengthy and undesirable address/cmd topologies.

Properly decouple the DDR2 chips per manufacturer recommendations. Typically, five low ESL capacitors per device are sufficient. For further information, see article entitled Decoupling Capacitor Calculation for a DDR Memory Channel, located on Micron’s web site.

To support expandability into larger devices, ensure that extra NC pins (future address pins) are connected.

Ensure access/test points are available for signal integrity probing. This is especially critical if using blind and buried vias within the memory channel. If through-hole vias are used under the BGA devices, then generally these sites can be used for probing.

Yes/No

.55.

56.57.

2Termination Dissipation

Power = I2 * RT = (18.6 mA)2 * (47 Ω) = 16.3 mW.

Sink and source currents flow through the parallel RT resistors on the address and control groups. The worst case power dissipation for these resistors is as follows:

Small compact 4-pin resistor packages (16 mm × 32 mm) that provide dissipation up to 1/16 watt (62.5 mW) are ideal. See Section4, “VTT Voltage Rail” for assumptions made for current calculations.

3VREF

The current requirements for VREF are relatively small, at less than 3 mA. This reference provides a DC bias of 0.9V (VDD/2) for the differential receivers at both the controller interface and the DDR devices. Noise or deviation in the VREF voltage can lead to potential timing errors, unwanted jitter, and erratic behavior on the memory bus. To avoid these problems, VREF noise must be kept within the JEDEC specification. As such, VREF and the VTT cannot be the same plane because of the DRAM VREF buffer sensitivity to the termination plane noise. However, both VREF and VTT must share a common source supply to ensure that both are derived from the same voltage plane. Proper decoupling at each VREF pin (at the controller, at each DIMM/discrete, and at the VREF source) along with the adhering to the simple layout considerations enumerated in the checklist prevents potential problems.

Numerous off-the-shelf power solutions can provide both the VREF and VTT from a common circuit. Regardless of the generation technique, VREF must track variations in VDDQ over voltage, temperature, and noise margins as required by the JEDEC specifications.

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

VTT Voltage Rail

For a given topology, the worst case VTT current should be derived. Assuming the use of a typical RT parallel termination resistor and the worst case parameters give in Table4-2, sink and source currents can be calculated.

Table4-2. Worst Case Parameters for VTT Current CalculationParameter

VDDQ(max)VTT(max)VTT(min)RDRVRRTVOL

Values

1.9 V0.958 V0.842 V10 Ω47 Ω0 V

Comment

From JEDEC spec From JEDEC specFrom JEDEC spec

Nominally, full strength is ~ 18 ΩsCan vary. Typically 25-47Ωs.

Assumes driver reaches 0 V in the low state.

The driver would source (VTT plane would sink) the following based on this termination scheme:

(VDD_max – VTT_min)/(RT + RDRVR) = (1.9 V – 0.842 V)/(47 + 10) = 18.6 mAThe driver would sink (VTT plane would source) the following based on this termination scheme:

(VTT_max – VOL / (RT + RS + RDRVR) = (0.958 V – 0 V)/(47+ 10) = 16.8 mAA bus with balanced number of high and low signals places no real demand on the VTT supply. However, a bus with all DDR address/command/control signals low (~ 28 signals) causes a transient current demand of approximately 500 mA on the VTT rail. The VTT regulator must provide a relatively tight voltage regulation of the rail per the JEDEC specification. Besides a tight tolerance, the regulator must also allow VTT along with VREF (if driven from a common IC), to track variations in VDDQ over voltage, temperature, and noise margins.

5Layout Guidelines for the Signal Groups

To help ensure that the DDR interface is properly optimized, Freescale recommends the following sequence for routing the DDR memory channel:1.Route data

2.3.4.5.

Route address/commandRoute controlRoute clocksRoute feedback

The data group is listed before the command, address, and control group because it operates at twice the clock speed and its signal integrity is of higher concern. In addition, the data group constitutes the largest portion of the memory bus and consists of most of the trace matching requirements, those of the data lanes. The address/command, control, and data groups all have a relationship to the routed clock. Therefore, the effective clock lengths used in the system must satisfy multiple relationships. The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Layout Guidelines for the Signal Groups

5.1Data—MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7]

The data signals of the DDR interface are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate.

An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing. Table5-3 depicts this relationship. When length matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the tDQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves.

Table5-3. Byte Lane to Data Strobe and Data Mask Mapping

DataMDQ[0:7]MDQ[8:15]MDQ[16:23]MDQ[24:31]MDQ[32:39]MDQ[40:47]MDQ[48:55]MDQ[56:63]MECC[0:7]

Data StrobeMDQS0, MDQS0MDQS1, MDQS1MDQS2, MDQS2MDQS3, MDQS3MDQS4, MDQS4MDQS5, MDQS5MDQS6, MDQS6MDQS7, MDQS7MDQS8, MDQS8

Data MaskMDM0MDM1MDM2MDM3MDM4MDM5MDM6MDM7MDM8

Lane Number

Lane 0Lane 1Lane 2Lane 3Lane 4Lane 5Lane 6Lane 7Lane 8

NOTE

When routing, each row (that is the 11-bit signal group) must be treated as a trace-matched group.

5.2Layout Recommendations

Freescale strongly recommends routing each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents, assisting the overall signal integrity of the data interface. This concern is especially critical in designs that target the top-end interface speed because the data switches at 2x the applied clock. When the byte lanes are routed, signals within a byte lane should be routed on the same critical layer as they traverse the PCB motherboard to the memories. This

consideration helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group.

To facilitate ease of break-out from the controller perspective, and to keep the signals within the byte group together, the board designer should alternate the byte lanes on different critical layers, (see Figure1 and Figure2).

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Layout Guidelines for the Signal Groups

Data Lane 7

Data Lane 5

Data Lane 3

Data Lane 1

Figure1. Alternating Data Byte Lanes on Different Critical Layers—Part 1

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Layout Guidelines for the Signal Groups

Data Group 6

Data Group 4

Data Group 8

Data Group 2

Data Group 0

Figure2. Alternating Data Byte Lanes on Different Critical Layers—Part 2

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2

Freescale Semiconductor

Simulation

6Simulation

This application note provides general hardware and layout considerations for hardware engineers imple-menting a DDR2 memory subsystem.The rules and recommendations in this document can serve as an initial baseline for board designers to begin their specific implementations. Numerous memory topolo-gies and interface frequencies are possible from the DDR2 interface, so Freescale highly recommends that the board designer verify that all aspects (signal integrity, electrical timings, and so on) are addressed through simulation before board fabrication.

In tandem with memory vendors, Freescale provides IBIS models for simulation. The board designer can realize a key advantage in the form of extra noise and timing margins by taking the following actions:•Optimizing the clock to signal group relationships to maximize setup and hold times.

•Optimizing termination values. During board simulation, verify that all aspects of the signal eye are satisfied, which includes at a minimum the following:

—A sufficient signal eye opening meeting both timing and AC input voltage levels—Vswing max not exceeded (or alternatively max overshoot/max undershoot)—Signal slew rate within specifications

Figure3. SSTL Signal Waveform

••